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Description:
Platform: | Size: 2048 | Author: 李涛 | Hits:

[VHDL-FPGA-Verilog] Example-b3-1

Description: 使用Quartus II设计FPGA的应用设计实例  “\Example-b3-1\uart_regs\src”目录下为设计源文件  “\Example-b3-1\uart_regs\core”目录下为Altera的IP宏功能模块  “\Example-b3-1\uart_regs\sim\funcsim”目录下为功能仿真文件  “\Example-b3-1\uart_regs\sim\parsim”目录下为时序仿真文件  “\Example-b3-1\uart_regs\dev”目录下为工程文件（包含了约束、综合、布局布线的过程文件和结果文件）
Platform: | Size: 397312 | Author: king | Hits:

[VHDL-FPGA-Verilog] ISP1362

Description: Verilog 编写的ISP1362的控制器IP核，altera公司DE2系统中的源程序-Verilog prepared ISP1362 controller IP core, altera company source DE2 System
Platform: | Size: 18432 | Author: zhyy | Hits:

[VHDL-FPGA-Verilog] logvhdl

Description: altera的关于对数计算的IP core。-altera calculated on the logarithm of the IP core.
Platform: | Size: 116736 | Author: max | Hits:

[Other Embeded program] 15alteraIP

Description: altera的15个IP核的源码，可能有用-altera of 15 IP-core source, may be useful
Platform: | Size: 49152 | Author: 谢一 | Hits:

[VHDL-FPGA-Verilog] atlf5Vcj

Description: 15个Altera的IP的源码,给大家分享下。-15 ?鯝ltera的IP的?#39 码, ??39 ???窒硐??
Platform: | Size: 50176 | Author: jkwzh | Hits:

[VHDL-FPGA-Verilog] lcd_com1

Description: 青云开发的LCD模块LCM240128ZK3用于ALTERA的FPGA，自己写的AVALON总线IP核，供大家参考-err
Platform: | Size: 4096 | Author: 张敏 | Hits:

[VHDL-FPGA-Verilog] xd_lcd_comp

Description: 一款240＊128的LCD模块在ALTERA　FPGA　NIOS中的应用，自己写的AVALON总线IP，包括所有源码，可轻松用于NIOS中，供大家参考-A 240* 128 LCD module in the ALTERA FPGA NIOS application, write your own AVALON Bus IP, including all source code can be easily used in NIOS for reference
Platform: | Size: 13312 | Author: 张敏 | Hits:

[VHDL-FPGA-Verilog] photo_verilog

Description: verilog开发的电子相册系统，是基于Altera的FPGA芯片和IP核的设计！-Verilog developed electronic album system is based on Altera s FPGA chip and IP core design!
Platform: | Size: 21504 | Author: sq | Hits:

[VHDL-FPGA-Verilog] AltrFir32

Description: 借助于altera公司的IP核，在FPGA中使用dspbuilder实现32位低通FIR滤波器功能，-Altera With the company
Platform: | Size: 9216 | Author: 齐磊 | Hits:

[VHDL-FPGA-Verilog] oc_i2c_master

Description: 这是一个I2C的IP。直接拷到altera公司的相应软件的目录下，即可应用。-This is an I2C of IP. Kaodao altera directly corresponding software company directory, can be applied.
Platform: | Size: 196608 | Author: 小杨 | Hits:

[matlab] altera_cic_compensate_ip

Description: 级联积分梳妆滤波器的补偿滤波器，altera公司IP-altera cic compensate filter
Platform: | Size: 3072 | Author: leexiao | Hits:

[VHDL-FPGA-Verilog] Example-s2-1

Description: 其中的EPLL、MY_DQ和MY_DQS模块是用Altera的IP产生器MegaWizard产生的-EPLL MY_DQ MY_DQS
Platform: | Size: 24576 | Author: 寻宝人 | Hits:

[Other] Source

Description: 15个Altera的IP的源码，很不错的，学习的好资料，-15 Altera' s IP source, it is good to learn good information, ha ha
Platform: | Size: 49152 | Author: sun | Hits:

[VHDL-FPGA-Verilog] mydds_rom

Description: 自己在参加altera NIOSii 软核设计大赛时编写的一个ip核，用于产生频率可调的正弦波-Their participation in the design of soft-core altera NIOSii the preparation of a competition when nuclear ip, used to generate the sine wave frequency adjustable
Platform: | Size: 21504 | Author: 刘小平 | Hits:

[VHDL-FPGA-Verilog] cw

Description: 用ip核设计的信号发生程序，altera的 用ip核设计的信号发生程序，altera的 用ip核设计的信号发生程序，altera的 用ip核设计的信号发生程序，altera的-signal source for altera by ip coresignal source for altera by ip coresignal source for altera by ip coresignal source for altera by ip coresignal source for altera by ip coresignal source for altera by ip core
Platform: | Size: 12539904 | Author: 李芳 | Hits:

[Other] pio_shiyan

Description: NIOS学习的例子，使用QUARTUS进行编辑和IDE共同实现的，使用ALTERA公司的内带IP完成例子。-NIOS study example, the use of QUARTUS common IDE for editing and realized within the company using ALTERA complete with examples of IP.
Platform: | Size: 4979712 | Author: 李华 | Hits:

[VHDL-FPGA-Verilog] DE2_pio

Description: altera University Program 的 Avalon总线的IP核，GPIO，可以直接解压以后挂载在Avalon总线上-altera University Program of the Avalon bus IP core, GPIO, after decompression can be directly mounted in the Avalon bus
Platform: | Size: 271360 | Author: vicky | Hits:

[VHDL-FPGA-Verilog] altera_up_avalon_ps2

Description: Altera公布的大学计划中基于VHDL的ps2的IP核！-Altera University Program announced VHDL-based IP core of the ps2!
Platform: | Size: 212992 | Author: 兔子 | Hits:

[VHDL-FPGA-Verilog] altera_up_flash_memory

Description: Altera公司大学计划中公布的基于VHDL的通用flash的IP核！-Altera' s University Program announced in the flash-based VHDL generic IP core!
Platform: | Size: 188416 | Author: 兔子 | Hits:
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